Job description
We are seeking a results-driven CPU DFT / MBIST Engineer to join PERSOL's engineering team in Singapore. This role focuses on developing robust design-for-testability (DFT) and memory built-in self-test (MBIST) solutions for CPU cores and related IP. You will work closely with RTL designers, EDA tools, and silicon bring-up teams to ensure high fault coverage, minimal test time, and successful production testing.
Responsibilities include owning end-to-end DFT/MBIST flows from specification through validation, implementing Scan chains, ATPG patterns, and pattern verification, and continuously optimizing test coverage and efficiency. You will analyze test failures, debug silicon issues, and provide actionable improvements to the test architecture. You will also contribute to test documentation, flows, and automation to scale the DFT capability across multiple CPU IP blocks.
The ideal candidate has hands-on experience with CPU IP DFT, strong knowledge of Scan, ATPG, and MBIST methodologies, proficiency with industry-standard EDA tools, and a collaborative mindset to work with cross-functional teams in a fast-paced environment. This role offers a competitive monthly salary, a supportive team culture, and opportunities to influence test strategies across CPU IP.
Responsibility
- Own and implement end-to-end DFT and MBIST flows for CPU cores and related IP blocks.
- Design, integrate, and optimize Scan chains to maximize observability while minimizing footprint.
- Develop ATPG patterns and pattern verification flows; verify fault coverage and test quality.
- Collaborate with RTL/design verification, EDA, and manufacturing teams to validate DFT implementations in simulation and silicon.
- Analyze test failures, debug DFT issues, and drive root-cause analysis and corrective actions.
- Create, maintain, and optimize test documentation, test benches, and automation scripts to scale DFT capabilities.
- Provide technical mentorship and assist in transferring knowledge to junior engineers and cross-site teams.
Qualification
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's preferred).
- Minimum 3 years of hands-on DFT/MBIST experience for CPU or SOC IP.
- Strong knowledge of Scan, ATPG, and MBIST methodologies; experience with industry tools (Mentor Tessent, Synopsys DFT Compiler/DFTMAX, etc.).
- Proficiency in scripting languages such as Python and TCL for automation.
- Solid debugging skills and experience with silicon bring-up and post-silicon test.
- Excellent communication, teamwork, and problem-solving abilities.