Job description
ByteDance invites talented Physical Design Engineers to join our Singapore hub and be part of the Silicon Platform Team—the core R&D middleware group driving chip development across the organization. This role focuses on translating RTL concepts into robust physical implementations, shaping floorplans, placements, routing, and sign-off strategies for leading-edge AI and multimedia silicon platforms.
ByteDance's Silicon Platform Team acts as the core R&D middleware group for chip development, overseeing the full RTL-to-GDSII flow and partnering with product and platform teams to deliver high-value silicon platforms powering ByteDance products globally. This is an exceptional opportunity to influence cutting-edge AI, media, and content-processing silicon used at scale.
As a Physical Design Engineer in Singapore, you will apply your expertise across all phases of the physical design flow. You will drive floorplanning, placement, clock tree synthesis, routing, and physical debugging, balancing timing, power, area, and reliability constraints. You will work with Design Teams to optimize memory blocks, standard cells, and IP blocks, ensuring robust sign-off with DRC/LVS clearance and power integrity checks. You will build and maintain scalable flows, scripts, and methodologies to improve efficiency and consistency across tape-outs.
This role requires collaboration with RTL engineers for timing closure, verification teams for post-layout validation, and hardware/software groups to align on manufacturing constraints. You should be comfortable using industry-standard EDA tools (e.g., Synopsys, Cadence, Mentor) and scripting languages (Python/Perl) to automate tasks and reproduce results. This is a unique chance to influence the architecture and manufacturing readiness of ByteDance's silicon platforms while growing leadership and technical skills in a dynamic, global environment.
Responsibility
- Drive the full physical design flow for ASIC blocks from floorplanning to sign-off, ensuring timing closure, reliability, and manufacturability.
- Plan and implement floorplanning, placement, clock-tree synthesis, routing, and optimization using industry-standard EDA tools.
- Collaborate with RTL, verification, and hardware teams to meet performance, power, and area targets across multiple silicon nodes.
- Perform power integrity checks, IR-drop analysis, DRC/LVS cleanup, and timing analysis (STA) to ensure robust tape-out readiness.
- Develop, maintain, and improve Python/Perl scripts and tool flows to increase design productivity and reproducibility.
- Debug and resolve layout-induced issues, perform cross-domain sign-off analyses, and prepare for manufacturing.
- Communicate findings effectively to multidisciplinary teams and mentor junior engineers as needed.
Qualification
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Proven experience with ASIC/SoC physical design flows, including floorplanning, placement, routing, and sign-off.
- Strong proficiency with industry EDA tools (e.g., Synopsys IC Compiler II/Genus, Cadence Innovus, Tempus, Mentor Signoff).
- Solid understanding of digital design, timing budgets, power integrity, clocking, and physical verification (DRC/LVS).
- Experience with scripting (Python, Perl) to automate flows and data analysis.
- Excellent problem-solving, debugging, and communication skills, with the ability to work effectively in cross-functional teams.
- Familiarity with memory blocks and IP integration is a plus; knowledge of silicon manufacturing constraints is beneficial.