Job description
Join Micron Semiconductors as a Sr. Manager Global Layout Asia and lead the strategic layout engineering across our Asia-Pacific operations. In this senior role, you will drive layout optimization, standardization, and collaboration with design, process, and manufacturing teams to ensure on-time product delivery and quality. You will oversee cross-functional programs, manage a high-performing team, and partner with regional stakeholders to translate product requirements into scalable layout solutions. This position offers the chance to influence next-generation memory and logic chip designs, shape layout methodologies, and mentor engineers across multiple sites.
As the Sr. Manager Global Layout Asia, you will own the end-to-end layout lifecycle—from planning and resource allocation to verification, DFM checks, and tape-out readiness. You will champion best practices in mask data preparation, parasitic extraction, and timing closure, while keeping a keen eye on cost, yield, and manufacturability. The successful candidate will demonstrate strategic leadership, advanced problem-solving, and exceptional communication to align diverse teams with business objectives.
We are seeking a results-oriented leader who thrives in a fast-paced semiconductor environment, comfortably navigating complex programs and global collaboration. If you are passionate about layout excellence and enabling product success in Asia, this is your chance to join a world-class organization that values innovation, quality, and growth.
Responsibility
- Lead and shape the Asia-based global layout strategy to meet product timelines and quality objectives.
- Direct a multi-site layout engineering team, setting priorities, mentoring staff, and driving performance metrics.
- Collaborate with design, process, and manufacturing teams to translate product requirements into scalable layout solutions.
- Oversee layout optimization, mask data preparation, parasitic extraction, DFM checks, and tape-out readiness.
- Establish and enforce standard work, design-for-manufacturability guidelines, and cross-functional design reviews.
- Manage budgets, resource planning, and stakeholder communications to ensure timely execution across regions.
Qualification
- Bachelor’s degree in Electrical Engineering, Materials Science, or a related field; Master’s preferred.
- 15+ years in semiconductor layout, verification, or design with leadership experience in global teams.
- Proven track record in mask layout, DFM, EDA tools, and complex integration flows.
- Strong project management, decision-making, and strategic planning capabilities.
- Excellent cross-functional communication and stakeholder management across Asia-Pacific regions.
- Travel willingness and ability to operate in a multinational, fast-paced environment.